Embedded System Design with Microblaze and Vitis IDE

Embedded System Design with Microblaze and Vitis IDE

Using Xilinx Vivado Design Suite and Vitis 2020.2

A faster Reconfigurable system makes FPGA a prominent choice for a large set of applications, but Hardware alone is incomplete without smart software synchronizing all the events fruitfully to achieve the desired Application. This course covers fundamentals of Popular Xilinx drivers viz. UART, AXI Timers, UART16550, AXI GPIO, AXI BRAM, etc. The course also illustrates the usage of the AXI interrupt controller for handling Interrupts. Also to felicitate incorporation of  Hardware accelerators with Microblaze based design few examples on building Custom AXI Peripherals are also included. Software and Hardware Debugging, Profiling fundamentals are demonstrated with Microblaze to felicitate performance measurement.

The Microblaze is an FPGA-based Soft Processor capable of executing single instruction per cycle with few exceptions. The MicroBlaze interconnect is reconfigurable capable of communicating with a large set of peripherals to fit most of the medium-scale applications. It allows configuration of cache size, pipeline depth, peripherals, memory management unit, and bus interface suitable to fit different application requirements. As systems complexities are growing day by day, Microblaze will play central role in the non-Zynq based FPGA families whereas it will be the best light-weight alternative working in tandem with the Zynq hard processor for Zynq and Ultrascale based FPGA families.

What you’ll learn?
  • Embedded System Design flow with Xilinx Vitis 2020.2
  • Designing Embedded System using Microblaze Soft Processor
  • Development of C applications for Microblaze Devices
  • Software and Hardware Debugging
  • Handling Interrupts in Microblaze based designs
  • Understanding Xilinx Drivers
Who is this course for?
  • Anyone wish to build expertise in Xilinx Microblaze Devices with Xilinx Vivado and Vitis IDE
  • Embedded System Design with FPGA Soft Processors
Requirements:
  • Understanding of Digital Electronics
  • Fundamentals of Computer Architecture
Course content
1. Getting Started
Agenda
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Design Flow Steps P1
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Design Flow Steps P2
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Design Flow Steps P3
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Fundamentals: Project Types
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Fundamentals P2: Flow Navigator
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Fundamentals P3: Useful files in Project Directory
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Fundamentals P3: How to update Hardware Platform P1
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Fundamentals P3: How to update Hardware Platform P2
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TCL Script for automation
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Different Reporting Mechanism
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2. Simple Peripherals
Agenda
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Fundamentals of XIL Drivers P1
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Fundamentals of XIL Drivers P2
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Fundamentals of XIL Drivers P3
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Writing Data to GPIO P1
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Writing Data to GPIO P2
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Writing Data to GPIO P3
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Reading Data from GPIO P1
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Reading Data from GPIO P2
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Using Dual Channel of GPIO P1
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Using Dual Channel of GPIO P2
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Multiple Instances of GPIO P1
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Multiple Instances of GPIO P2
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3. Intermediate Peripherals
Agenda
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Sending Data to UART P1
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Sending Data to UART P2
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Receiving Data from UART
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Multiple Instance of UARTLITE P1
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Multiple Instance of UARTLITE P2
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4. Working with Timers
Agenda
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Using AXI Timer P1
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Using AXI Timer P2
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How we observe the Current Count Value
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Using Auto Reload Mode
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Using both Timers
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Using PWM: 50% Duty Cycle P1
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Using PWM: 50% Duty Cycle P2
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Using PWM: 50% Duty Cycle P3
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Varying Duty Cycle
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Fading Effect
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AXI Timebase Watchdog Timer P1
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AXI Timebase Watchdog Timer P2
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Mulitple Event with WDT
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5. Profiling
Agenda
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Profile with AXI Timer P1
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Profile with AXI Timer P2
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SDK Profiler P1
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SDK Profiler P2
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6. Memory Resources
Understanding Byte Addressable and Word Addressable
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Adding BRAM IP to Block Design
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BRAM Transactions using pointers
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BRAM Transactions using XIL_IO Drivers
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7. Debugging Technique
Hardware Debugging: Integrated Logic Analyzer P1
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Hardware Debugging: Integrated Logic Analyzer P2
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Hardware Debugging: Integrated Logic Analyzer P3
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Software Debugging: Serial Window
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8. Interrupts
Agenda
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Interrupt with GPIO P1
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Interrupt with GPIO P2
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AXI Timer Interrupt P1
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AXI Timer Interrupt P2
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Interrupt with WDT P1
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Interrupt with WDT P2
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Reset with WDT
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9. Building Custom AXI Peripherals for Microblaze
Agenda
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Create SLAVE AXI LITE Interface P1
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Create SLAVE AXI LITE Interface P2
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Adding Port to Slave AXI LITE Interface P1
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Adding Port to Slave AXI LITE Interface P2
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Adding Port to Slave AXI LITE Interface P3
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Create AXI Stream Interface P1
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Create AXI Stream Interface P2
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